1. Field of the Invention
The present invention relates to semiconductor memories (e.g., RAM or ROM memories), and more particularly, to a bit line sense amplifying circuit for use in a semiconductor memory for effectively transmitting or receiving data from a bit line pair to an input/output line pair in a data read or write operation at a low supply voltage level.
2. Description of the Related Art
Recently, semiconductor memories requiring only a low supply voltage level have been popularized. As the supply voltage level of the semiconductor memories becomes lower, data sensed from a memory cell is transmitted from a bit line pair to an input/output line pair under the influence of the lowered supply voltage. At these lower voltages, the resistance to current between the bit line pair and the input/output line pair has a greater affect upon the performance of the memories.
FIG. 1 is a circuit diagram of a conventional circuit including a direct sense AMP that connects a data input/output pair to a bit line pair.
Referring to FIG. 1, a first bit line BL is connected to a second data output line RIOB through a transistor TR3 of a direct sense AMP 150. A second bit line BLB is connected to a first data output line RIO through a transistor TR2 of the direct sense AMP 150.
The first bit line BL is connected to a first data input line WIO through a transistor TR4, and the second bit line BLB is connected to a second data input line WIOB through a transistor TR5.
In a data read operation, if a column address signal CAS and a write command WR are at a high level, a read command signal CSLR is applied to the transistor TR1 at a high level, and thus the Sense AMP 150 is activated, and the transistor TR1 is turned ON (meaning active, conducting current). At least one of the Sense Amp transistors TR2 or TR3 detects the minute voltage signal on its respective bit line (BL or BLB) and “amplifies” it. Then, data in the bit line pair (BL and BLB) is output to first and second output lines (RIO and RIOB). In a data read operation, a write signal CSLW becomes low, and thus the transistors TR4 and TR5 are turned OFF.
In a data write operation, if the column address signal CAS is at a high level, and the write command WR is at a low level, the read command signal CSLR becomes low and is applied to the transistor TR1, and thus the transistor TR1 is turned OFF. Therefore, the direct sense AMP 150 does not operate. The write signal CSLW becomes high, and thus the transistors TR4 and TR5 are turned ON. Then, data is input to the bit line pair BL and BLB through the first and second data input lines WIO and WIOB.
In FIG. 1, a data output line pair (RIO and RIOB) and the data input line pair (WIO and WIOB) are separate from each other.
FIG. 2 is a circuit diagram of another conventional circuit including a sense AMP that connects a data input/output line pair to a bit line pair.
A circuit 200 of FIG. 2 has the same configuration as a circuit 100 of FIG. 1 except that it has a data input/output line pair DIO and DIOB where the data output line pair RIO and RIOB and the input line pair WIO and WIOB of FIG. 1 are directly connected to each other.
Similarly to the circuit 100 of FIG. 1, in a data read operation, the transistor TR1 is turned ON, and the transistors TR4 and TR5 are turned OFF. Thus, data of the bit line pair BL and BLB is output to the data input/output pair DIO and DIOB.
In a data write operation, the transistor TR1 is turned OFF, and the transistors TR4 and TR5 are turned ON. Thus, external data is input to the bit line pair BL and BLB through the data input/output line pair DIO and DIOB.
However, in the data read operation involving the conventional sense AMPs (150 and 250) of FIGS. 1 and 2, only the read command signal CSLR is activated, and data amplified by sense AMPs (150 and 250) is transmitted to the data input/output pair DIO and DIOB. In the data write operation, only the write signal CSLW is activated, and external data input from DIO and DIOB through the transistors TR4 and TR5 is transmitted to the bit line pair BL and BLB.
Since only the read command signal CSLR is activated in the data read operation, the data input/output line pair DIO and DIOB are affected by only the sense AMPs 150 and 250. During the data read operation the data lines extending between the bit line pair BL and BLB and the transistors TR4 and TR5 respectively, are electrically disconnected from the data input/output line pair DIO and DIOB by transistors TR4 and TR5 in the OFF state. Thus, the data input/output line pair DIO and DIOB is not affected by the data lines extending between the bit line pair BL and BLB and the transistors TR4 and TR5 respectively.
Therefore, if the sense AMP 250 alone is activated for a data read operation in the semiconductor circuit of FIG. 2 whose supply voltage level is low, it is difficult (e.g., slow) to execute the data read operation.